`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:53:40 12/09/2008 
// Design Name: 
// Module Name:    TESTRAM2 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module TESTRAM2(
	 input invClock,
	 input [14:0] VGAaddress,
	 output reg [15:0] vgaData
    );
  parameter RAM_WIDTH = 16;
  parameter RAM_ADDR_BITS = 14;

  reg [RAM_WIDTH-1:0] test [(2**RAM_ADDR_BITS)-1:0];
  
//  The following code is only necessary if you wish to initialize the RAM
//  contents via an external file (use $readmemb for binary data)
  initial
  $readmemh("fib.dat", test, 14'd0, 14'd16383);

  always @(posedge invClock)
  begin
			vgaData <= test[VGAaddress];
		
	end
endmodule
